Specifically, the present invention relates to an electronic memory apparatus for storing data, having:
a) a memory cell array which has memory cells arranged in rows and columns;
b) a column address decoding unit for decoding a column addressing signal and for actuating an addressed bit line in the memory cell array;
c) a column redundancy activation unit for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus;
d) a row address decoding unit for decoding a row addressing signal and for actuating an addressed word line in the memory cell array; and
e) a row redundancy activation unit for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus.
As circuit size and circuit complexity increase, an increasing number of components, for example transistors, are produced on a single circuit chip (electronic circuit unit). In this case, problems are caused by an operating current increasing with the number of components, since this results in an increase in the power loss from the overall circuit arrangement. It is therefore necessary to reduce the power loss from the individual structures upon a further reduction in the size of circuit structures and an associated increase in the scale of integration for circuits.
FIG. 2 shows a memory cell array based on the prior art. The memory cell array is addressed by addressing signals (column addressing signal SAS, row addressing signal ZAS). A column decoder Col. dec. or a row decoder Row dec. decode the respective addressing signals and supply them to the memory cell array (Array).
To improve reliability of the memory module and/or to provide a repair option for faulty bit lines and/or word lines, it has been found to be advantageous in the case of the conventional circuit arrangement for redundancy activation circuits RA to be provided which activate redundant bit lines and/or word lines when a currently used bit line and/or word line is faulty. It is also possible to switch from a currently used bit line and/or word line to a redundant bit line or word line when a fault occurs in a memory cell area of the memory cell array which is associated with the bit line or word line.
It should be pointed out that redundant bit lines or word lines are provided not only in memory modules but also in numerous other electronic components in order to be able to repair faulty bit lines or word lines. In this case, accessing addresses for faulty bit lines and word lines involves only the addresses being switched, i.e. rerouted to redundant bit lines and word lines. The faulty bit lines and word lines and the associated circuit parts are disadvantageously also supplied with a current. In this case, the “bleeder circuits” have a small leakage current continually flowing through them, since in a memory module such bleeder circuits are used to pull bit lines or word lines to a predetermined potential and to keep them there for as long as the corresponding bit line or word line is not being addressed.
When the electronic memory apparatus has been tested at wafer level, the bit lines and word lines identified as being faulty are replaced with redundant bit lines and word lines. Although the faulty bit lines and word lines and the bit lines and word lines which are not brought in, i.e. not used, for repair are not used for correct circuit operation of the memory module or of the electronic memory apparatus, they disadvantageously cause a leakage current. Such a leakage current can disadvantageously cause power loss when there are a large number of unused and/or faulty bit lines.
The reason for this is that a bit line which has been identified as being faulty during testing of the electronic memory apparatus at wafer level has, by way of example, a short circuit to ground potential or to a supply voltage potential.
Another drawback is that determining whether it is necessary to use a redundant bit line to which addresses have been rerouted requires additional determination time. The reason for this is that it is first necessary to check whether an appropriately addressed bit line or word line or the previously determined redundant bit line and/or word line needs to be activated. Following such determination, only the correspondingly selected bit line and/or word line can be activated, while the other bit line and/or word line needs to be disconnected.
An electronic memory apparatus based on the prior art, as shown in FIG. 2, for example, has a large number of bit lines and/or word lines which are not deactivated. Unused bit lines and/or word lines or faulty bit lines and/or word lines thus cause a problem in that a large leakage current results in high power loss. Another drawback is that activation is possible only after the relevant bit line and/or word line has been determined by an evaluation value unit.